Test apparatus and operating method thereof

ABSTRACT

A test apparatus includes a test apparatus may include a core suitable for accommodating a semiconductor device to be tested, a wrapper data register suitable for storing data used for testing the semiconductor device, and a bandwidth controller suitable for adaptively controlling a data bandwidth between the core and the wrapper data register according to the semiconductor device to be tested.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No.10-2013-0071000, filed on Jun. 20, 2013, which is incorporated herein byreference in its entirety.

BACKGROUND

1. Field

Exemplary embodiments of the present invention relate to a semiconductordesign technology, and more particularly, to a test apparatus fortesting a semiconductor device, and a method thereof.

2. Description of the Related Art

Electronic appliances which are produced in these days may be designedto perform a smart operation in order to meet the needs of consumer. Toimplement this operation, various semiconductor chips such as amicroprocessor, a networking chip, a memory, or the like are provided inthe electronic appliances, and a secure and fast communication betweenthe semiconductor chips in the electronic appliances may be moreimportant due to complex and diverse trends of the electric appliances.

A System on Chip (SoC) technique is emerging that a plurality ofsemiconductor chips are organically connected and act as a single chip.In the SoC technique, a microprocessor, a digital processor, a memory, abaseband chip and the like are integrated in a single chip so that thesingle chip itself may function as a system. The SoC technique may havemany advantages in terms of system cost and size of circuits, and theSoC technique may be expanding throughout an Information Technology (IT)industry as well as a semiconductor industry due to those advantages.

In the SoC technique, a memory and a non-memory required for a systemare integrated in a single chip. A distinction between companies formanufacturing, production, and design of the SoC is becoming ambiguous,and thus the overall technical and market competition is getting fierce.In particular, since the SOC technique essentially requires ananometer-scale deep-submicron process technology and a softwaretechnology, a competition to secure those technologies is expected tobecome more intense.

Meanwhile, due to a development of a semiconductor manufacturingtechnology and a design technology, high-performance products arepossible to be produced. At this time, to test circuits inside a SoC,additional configurations are required as follows.

First, the existing test equipment may not be used in the SoC technologysince concerns such as noise, signal delay, interference, and the likebecome important due to an ultra-fine process. Accordingly, a cost topurchase a new test apparatus and a time for developing the desired testmay be required. Further, it may be difficult to test the SoC since itmay be difficult to acquire interconnections required for a test betweenan input/output of the SoC between an input/output of core. In otherwords, plural cores are built inside the SoC but it may be difficult toseparately provide each core with a respective pin for the test. Thus, atest apparatus and a test method are required to test the plural coresprovided inside the SoC by using minimal test pins.

In the end, because it may be difficult to acquire additional pinsrequired for testing the plural cores, and to couple an input/output ofthe SoC with inputs/outputs of the plural cores, a test apparatus fortesting the SoC requires a unique test structure.

Meanwhile, a plurality of cores are provided in the SoC, and the coresare coupled to each other by a plurality of connecting lines. In theconventional SoC, it may be enough to test the SoC by testing staticfaults such as a stuck-at fault, an open-net fault, a shorted-net fault,or the like since reliability of a data transfer is only checkedregardless of checking a speed during testing the connecting lines.However, in case of an SoC operating at a high speed, an additional testoperation may require since a signal delay of the connecting linescauses the entire SoC to malfunction.

SUMMARY

Various exemplary embodiments of the present invention are directed to atest apparatus for testing a semiconductor device, and a method thereof,capable of performing various test operations on a System on Chip (SoC).

In accordance with an exemplary embodiment of the present invention, atest apparatus may include a core suitable for accommodating asemiconductor device to be tested, a wrapper data register suitable forstoring data used for testing the semiconductor device, and a bandwidthcontroller suitable for adaptively controlling a data bandwidth betweenthe core and the wrapper data register according to the semiconductordevice to be tested.

In accordance with an exemplary embodiment of the present invention, atest apparatus may include a core suitable for accommodatingsemiconductor devices to be tested, a plurality of data registerscorresponding to the semiconductor devices, suitable for storing datarequired for a respective test operation of the semiconductor devices, acommon data register suitable for storing data required for a commontest operation of the semiconductor devices, and a wrapper commandregister suitable for adaptively controlling the test operations of theplurality of data registers and the common data register.

In accordance with an exemplary embodiment of the present invention, amethod of operating a test apparatus may include performing a first testoperation on a first semiconductor device based on a first databandwidth corresponding to the first semiconductor device, performing asecond test operation on a second semiconductor device based on a seconddata bandwidth corresponding to the second semiconductor device, andperforming a common test operation on the first and second semiconductordevices based on data stored on a common data register.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a test apparatus in accordancewith an exemplary embodiment of the present invention.

FIG. 2 is a block diagram illustrating a test apparatus in accordancewith another exemplary embodiment of the present invention.

FIG. 3 is a diagram illustrating a common test data resister shown inFIG. 2.

DETAILED DESCRIPTION

Various exemplary embodiments of the present invention will be describedbelow in more detail with reference to the accompanying drawings. Thepresent invention may, however, be embodied in different forms andshould not be construed as limited to the embodiments set forth herein.Rather, these embodiments are provided so that this disclosure will bethorough and complete, and will fully convey the scope of the presentinvention to those skilled in the art. Throughout the disclosure,reference numerals correspond directly to the like numbered parts in thevarious figures and embodiments of the present invention. It is alsonoted that in this specification, “connected/coupled” refers to onecomponent not only directly coupling another component but alsoindirectly coupling another component through an intermediate component.In addition, a singular form may include a plural form as long as it isnot specifically mentioned in a sentence.

FIG. 1 is a block diagram illustrating a test apparatus in accordancewith an exemplary embodiment of the present invention.

Referring to FIG. 1, the test apparatus includes an input wrapperboundary register (WBR) 110, an output wrapper boundary register (WBR)120, a core 130, a bandwidth controller 140, a wrapper data register150, and a multiplexer 160.

The input WBR 110 and the output WBR 120 serve to perform a paralleltest operation of the core 130, and serve to interface between the core130 and the external. The core 130 includes a region where asemiconductor device to be tested is disposed. Thus, the core 130 mayaccommodate the semiconductor device to be tested. The bandwidthcontroller 140 controls a data bandwidth between the core 130 and thewrapper data register 150 in response to a bandwidth control signalCTR_BW. Hereinafter, the data bandwidth between the core 130 and thewrapper data register 150 is referred to as a ‘test input/outputbandwidth’. Here, the bandwidth control signal CTR_BW includesinformation about the test input/output bandwidth of the semiconductordevice to be tested. The wrapper data register 150 stores datatransferred through a wrapper serial input signal WSI. The stored dataare transferred to the semiconductor device accommodated in the core 130under the control of the bandwidth controller 140 to be used during thetest. The multiplexer 160 outputs a wrapper serial output signal WSO byselecting one of a boundary test operation result of the input WBR 110and the output WBR 120, and a test operation result of the wrapper dataregister 150.

Hereinafter, an operation of the test apparatus is described in detail.For illustrative purposes, a process for transferring data transferredthrough the wrapper serial input signal WSI to the core 130 is describedas a representative.

First, the data for testing the semiconductor device included in thecore 130 are transferred through the wrapper serial input signal WSI,and stored in the wrapper data register 150. Meanwhile, a first signalgroup DAT1<0:M> outputted from the wrapper data register 150 hasbandwidth identical to a maximum test input/output bandwidth (M+1) ofthe semiconductor device to be tested, where M represents a positiveinteger. Subsequently, the bandwidth controller 140 receives and adjuststhe first signal group DAT1<0:m> to the test input/output bandwidth ofthe semiconductor device to be tested, and outputs a second signal groupDAT2<0:N> in response to the bandwidth control signal CTR_BW, where N isa positive integer less than or identical to M. As a result, thesemiconductor device to be tested may perform a test operation based onthe second signal group DAT2<0:N> corresponding to its test input/outputbandwidth.

The test apparatus in accordance with the exemplary embodiment mayadaptively control the test input/output bandwidth between the core 130and the wrapper data register 150, according to the semiconductor deviceto be tested. That is, the test apparatus may test a respectivesemiconductor device using an optimized test input/output bandwidth.

For reference, although the exemplary embodiment explains a case wherethe data stored in the wrapper data register 150 is transferred to thecore 130 as an example, a case where a test operation is performed inthe core 130, and the test result is transferred to the wrapper dataregister 150 from the core 130 may be applicable. That is, the testinput/output bandwidth may be defined in consideration of input data andoutput data

FIG. 2 is a block diagram illustrating a test apparatus in accordancewith another exemplary embodiment of the present invention.

Referring to FIG. 2, the test apparatus includes an input wrapperboundary register (WBR) 210, an output wrapper boundary register (WBR)220, a core 230, a plurality of wrapper data registers 240, a commontest data register 250, a wrapper bypass register 260, a wrapper commandregister 270, a multiplexer 280, and a test controller 290.

The input WBR 210 and the output WBR 220 serve to perform a paralleltest operation of the core 230, and serve to interface between the core230 and the external. The core 230 includes a region where asemiconductor device to be tested are disposed. Thus, the core 230 mayaccommodate the semiconductor device to be tested. In the core 230,homo-semiconductor devices or hetero-semiconductor devices may bedisposed in the core 230. Here, the hetero-semiconductor devices denotea case where a plurality of semiconductor chips which operate insynchronization with different clocks from each other are disposed in aSoC, and the homo-semiconductor devices denote a case where at least onesemiconductor chip which operates in synchronization with a clock isdisposed in a SoC.

The plurality of wrapper data registers 240 store data required for arespective test operation of the semiconductor to be tested, and thecommon test data register 250 stores data required for a common testoperation of the semiconductor devices to be tested. For example, wheneach of first and second semiconductor device is tested, two in theplurality of wrapper data registers 240 are provided for first andsecond test operations of the first and second semiconductor devices,respectively, and the common test data register 250 is provided for thecommon test operation of the first and second semiconductor devices. Adata bandwidth of the common test data register 250 may be differentfrom a data bandwidth of the plurality of wrapper data registers 240.

The wrapper bypass register 260 forms a bypass path between a wrapperserial input signal WSI and a wrapper serial output signal WSO. Thewrapper command register 270 controls the plurality of wrapper dataregisters 240 and the common test data register 250 to test thesemiconductor device disposed in the core 230.

The test controller 290 controls the input WBR 210, the plurality ofwrapper data registers 240, the common test data register 250, thewrapper bypass register 260, and the wrapper command register 270 bygenerating control signals for controlling operations of the registers,such as CAPTUREDR, UPDATEDR, SHIFTDR, CAPUTREIR, UPDATEIR, and SHIFTIR,a test clock WRCK for the registers, and a reset signal WRST, inresponse to a test clock P_TCK, a test mode signal P_TMS, and a testreset signal P_TRST. According to the signals generated by the testcontroller 290, one of the plurality of wrapper data registers 240 andthe common test data register 250 is activated. The multiplexer 280outputs the wrapper serial output signal WSO by selecting one output ofthe output WBR 220, the plurality of wrapper data registers 240, thecommon test data register 250, and the wrapper bypass register 260.

As described above, the test apparatus in accordance with the embodimentmay perform a respective test operation corresponding to one of thesemiconductor devices disposed in the core 230, and may perform a commontest operation corresponding to the semiconductor devices to be tested.

FIG. 3 is a diagram illustrating the common test data resister 250 shownin FIG. 2.

For illustrative purposes, a case of the common test data resister 250having 15 data cells is described as a representative.

Referring to FIG. 3, the common test data register 250 includes circuitsfor storing a timing information TM_ENT of the test operation, addressesA<0:7> for setting various test modes, a test result informationDET<0:1>, and a data information DQ<0:3> about data which areinputted/outputted during the test operation. As illustrated in FIG. 2,the common test data register 250 stores data required for the commontest operation of the semiconductor devices to be tested.

Accordingly, the test apparatus in accordance with the embodiment mayperform the common test operation of the semiconductor devices to betested using the common test data register 250.

As described above, the test apparatus in accordance with the embodimentmay detect information about a test input/output bandwidth of asemiconductor device to be tested. Further, the test apparatus inaccordance with the exemplary embodiment may select a correspondingregister in response to the information, and thus a test input/outputbandwidth between the semiconductor device and the register may beoptimized according to the semiconductor device to be tested.

Furthermore, the test apparatus in accordance with the embodiment mayaccurately analyze a failure to the semiconductor device to be testedaccording to various test result.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

What is claimed is:
 1. A test apparatus comprising: a core suitable foraccommodating a semiconductor device to be tested; a wrapper boundaryregister suitable for performing a parallel test operation of thesemiconductor device; a wrapper data register suitable for storing datatransferred through a wrapper serial input signal and used for testingthe semiconductor device; and a bandwidth controller suitable foradaptively controlling a data bandwidth between the core and the wrapperdata register according to the semiconductor device to be tested.
 2. Thetest apparatus of claim 1, wherein the bandwidth controller is suitablefor controlling the data bandwidth in response to a control signalhaving information corresponding to the semiconductor device to betested.
 3. The test apparatus of claim 1, wherein data between the coreand the bandwidth controller have a first bandwidth, and data betweenthe bandwidth controller and the wrapper data register have a secondbandwidth, the first bandwidth being less than or identical to thesecond bandwidth.
 4. A test apparatus comprising: a core suitable foraccommodating semiconductor devices to be tested; a plurality of dataregisters corresponding to the semiconductor devices, suitable forstoring data required for a respective test operation of thesemiconductor devices; a common data register suitable for storing datarequired for a common test operation of the semiconductor devices,wherein one of the plurality of wrapper data registers and the commontest data register is activated, and a data bandwidth of the common dataregister is different from a data bandwidth of the plurality of dataregisters; and a wrapper command register suitable for adaptivelycontrolling the test operations of the plurality of data registers andthe common data register according to the semiconductor devices to betested.
 5. The test apparatus of claim 4, further comprising: a wrapperboundary register suitable for performing a parallel test operation ofthe semiconductor devices; and a wrapper bypass register for forming abypass path between input data and output data of the semiconductordevices, wherein one of the plurality of wrapper data registers, thecommon test data register, the wrapper boundary register, and thewrapper bypass register is activated.
 6. The test apparatus of claim 1,wherein the common data register stores timing information of the testoperations, address information for setting test modes, and test datainformation corresponding to data which are inputted/outputted duringthe test operations.
 7. A method of operating a test apparatus, themethod comprising: performing a first test operation on a firstsemiconductor device based on a first data bandwidth corresponding tothe first semiconductor device; performing a second test operation on asecond semiconductor device based on a second data bandwidthcorresponding to the second semiconductor device; and performing acommon test operation on the first and second semiconductor devicesbased on data stored on a common data register, wherein a data bandwidthof the common test operation is different from data bandwidths of thefirst test operation and the second test operation.
 8. The method ofclaim 7, wherein the common data register stores timing information ofthe test operations, address information for setting test modes, andtest data information corresponding to data which are inputted/outputtedduring the test operations.